MegaSquirt-II Sequencer™ CPLD

The ignition routing on the Sequencer™ is a bit complicated, with the addition of a CPLD (complex programmable logic device). The MS-II™ processor has the capability of spark resolution at 2/3 of a microsecond, and we want to maintain this if at all possible. I have been involved with some really high-revving engines (13K+) with MicroSquirt^®, and performing ignition timing studies, and 1-degree control makes measurable power difference at high speed. I have data that shows that MicroSquirt^® (at 2/3 uS ignition) matches exactly the results from a Motec unit all they up beyond 13000 RPM (Motec uses the 68332 TPU which has a 2 uS resolution - it is a really good system).

OK, with MicroSquirt^® there are two ignition output channels that ping-pong back and forth.

One thing Al found on the original sequencer board had to do with the way we were routing the spark outputs. If you recall, we used AND gates to steer the two ignition channels to the ignition outputs, example ignition channel one to outputs 1-4 and ignition 2 to 5-8. The issue that Al found was with the six cylinder arrangement. The problem was switching from wasted spark to sequential - there are two spark outputs from the processor, but in wasted spark mode there are three routes to channel 1,2,3, so it was hard to ping-pong between the two ignition channels (1,2,1,2,1,2,1,2) and route to the odd number of 3 (1,2,3,1,2,3) with the old AND gate logic.

After screwing around with extra external logic gates, we decided to bite the bullet and put down a CPLD. We are using the MAX3000 series from Altera - it's cheap (under $2.00) and has enough logic gates to do what we want. The downside is that this part is a 3.3v device, so we had to put down a 3.3v regulator. The output of the CPLD (spark outputs) go to a TTL buffer, and 3.3V logic will drive TTL just fine, so we end up with 5V outputs. For the inputs to the CPLD (the 8 control lines for the modes) Al is running the HCS12 in a "open-drain" mode where he either puts out a logic zero, or configures the HCS12 as an input and lets the CPLD pullup resistors to pull up to 3.3V.

These two channels, via the Altera CPLD, get routed to one of 8 outputs, using two identical 2-to-8 decoders, one for each ignition channel. From the second 9S12C64 router processor there are eight control signals that go to the CPLD. The first three lines control the first 2-8 decoder via a binary control (control 000 routes to first ignition output, 001 routes to the second one,....,111 routes to the eighth one). The second three lines control the second 2-8 decoder for the second ignition channel - it can route to output 1-8. The final two control lines is for wasted spark mode. For instance, for a 4-cylinder wasted spark, output 3 needs to mirror output 1 and output 4 needs to mirror output2. Same for 6 and 8-cylinder mode. So, these last two control lines control this - logic 00 means no mirroring (COP-mode), logic 01 means 4-cylinder, logic 10 means 6-cyl, and logic 11 means 8-cylinder output mirroring.

The CPLD has 64 logic elements ("LE"), all of the router logic only chewed up 12 LE in the Quartus tools, so we have a lot more to use if we want.

Now, the CPLD is a 3.3V device, from the MAX3000 family. Very inexpensive (like in the $2.00 range inexpensive), but one has to play tricks with interfacing to 5V logic from the two 9S12C64 processors. First, there is a 3.3V supply for the CPLD, a LT1117 (Linear Tech) handles this small amount of current. Next, logic outputs are 3.3V, but we need TTL-level signals for the ignition outputs, so we are using a 5V buffer chip. This chip is TTL logic level so a logic high of 3.3V input is considered a logic high for TTL 5V - CMOS inputs would not work.

The ignition and control lines from the two 9S12C64 processors are 5V, and just hooking them up to the CPLD would not be good. The CPLD has internal body diodes that will sink/source current if the input is below 0 volts or above 3.3V. Feeding 5V into the 3.3V input would turn the body diodes on and without any current limiting the Altera would overheat from the free-flowing current. So, the two ignition channels from the MS-II™ processor route thru series resistors to limit current, and to keep the rise times short.

Now, the 8 control lines from the router processor also need limiting as well. But - there is simply no more room left on the board for 8 resistors. So, we are using a little trick. The HCS12 processor ports can be configured as inputs or outputs, and there are internal 50K pullup resistors (really current sources). So what is done is to run the 9S12C64 in "open-drain" mode. What is done is to set the output register to zero. Next, the pull-ups are enabled. Then, the data-direction register on the 9S12C64 processor is used to control the output. For a logic zero, the port is configured as an output, and since there is a zero in the data register the output is a zero. For a logic one, the data direction register sets the processor port as an *input*, so there is no drive - but the pullup resistors raise the output port to 5V. The pullup resistors limit the current flowing into the CPLD, and we are good.

There are two additional control lines from the router processor to the CPLD used for "spares" (any good designer will take all unused processor lines and route to an FPGA/CPLD for later use - programmable logic are useful creatures for hardware changes later on.). And we have gobbled one of the spares up - we realized at out of reset the router processor will take a small amount of time to set the port up correctly, but during this time the CPLD can float to any routing configuration. So we are using a spare line as an CPLD output enable such that the 8 ignition outputs will come up disabled. The spare line has an external pullup to force a logic 1 at powerup, and we set logic zero to enable the outputs of the CPLD.

Note that with the CPLD, it is possible to not use two 9S12C64 chips but one 9S12C64 chip in a bigger package and dedicate 8 signals to control the router. The two-chip setup right now is for us to take advantage of the huge stockpile of 9S12C64 chips we have on hand. We probably will later re-layout to a larger package (and XGATE compatible). But the advantage here is that the CPLD allows us to take two timer channels and maintain the timing accuracy to eight outputs, and easily switch between wasted and COP.